1. Field of the Invention
The present invention relates to the receiver circuitry of devices connected to a transmission line and, in particular, to a circuit for equalizing varying lengths of transmission line.
2. Description of the Related Art
A length of transmission line, which is in excess of a minimum length, attenuates the high-frequency components of a data signal transmitted across the transmission line. The degree of high-frequency attenuation is dependent upon the length of the transmission line and can be mathematically represented as a transfer function.
An equalization amplifier is a device that compensates the data signal for frequency attenuation. The frequency effect of the equalization amplifier can also be mathematically represented as a transfer function. Thus, by forming an equalization amplifier which has a transfer function which is approximately the inverse of the transfer function of the transmission line, substantially all of the high-frequency components attenuated by the transmission line can be recovered.
FIG. 1 shows a schematic of one example of a equalization amplifier 2 based upon a differential pair configuration. As shown in FIG. 1, the differential pair generates a pair of complementary output signals Veo+/- in response to a pair of complementary input signals Vei+/-.
The differential pair includes a first input transistor T1, a second input transistor T2, and an inverse transfer function generator 4. Transistor T1 has its base connected to receive the positive input signal Vei+, its collector connected to a power supply through a first output resistor Reel, and its emitter connected to ground through a first current source Iec1.
Transistor T2 has its base connected to receive the negative input signal Vei-, its collector connected to the power supply through a second output resistor Rec2, and its emitter connected to ground through a second current source Iec2. Transistors T1 and T2 are biased by current sources Iec1 and Iec2 and collector load resistors Ree1 and Rec2 for linear operation as a differential amplifier.
The inverse transfer function generator 4 includes an emitter resistor Re1, a first capacitor Ce1, and a second capacitor Ce2 and a transfer resistor Re2 connected in series with the second capacitor Ce2, each of which are connected between the emitter of input transistor T1 and the emitter of input transistor T2.
The voltage transfer function of equalization amplifier 2 can be determined by first considering a circuit which is a simplified model of the FIG. 1 circuit. FIG. 2 shows a simplified, medium-frequency, small-signal circuit diagram which is equivalent to one-half of the differential pair illustrated in FIG. 1. Using the concept of symmetry, associated with the balanced driving of a differential amplifier, and given the practical assumptions that the impedance Z(s) &gt;&gt;1/g.sub.m for the frequency range of the application, that g.sub.m =I.sub.ec1 q/K.sub.T =I.sub.ec1 /0.0259 @27.degree. C., and that r.sub..pi. =.beta./g.sub.m, the voltage transfer function Vout/Vin can be calculated to equal: ##EQU1##
The impedance Z(s) can be determined by first considering a circuit which is a symmetrical equivalent to inverse transfer function generator 4 of the FIG. 1 circuit. FIG. 3 shows a point of symmetry circuit diagram which is equivalent to inverse transfer function generator 4 of FIG. 1. As shown in FIG. 3, the values of Re1 and Re2 have each been divided by half and divided equally around a point of symmetry line, while Ce1 and Ce2 have been doubled and divided equally around the point of symmetry line 6.
The impedance Z(s) is next determined by considering one side of the FIG. 3 circuit. FIG. 4 shows a circuit diagram illustrating one side of the FIG. 3 circuit. As shown in FIG. 4, Z(s) is a complex impedance composed of resistors R1 and R2 and capacitors C1 and C2 where R1=Re1/2, R2=Re2/2, C1=2*Ce1 and C2=2*Ce2. The actual driving point impedance for Z(s) can then be described by: ##EQU2##
Again, given assumptions practical for this application, the impedance Z(s) can be simplified and described by: ##EQU3## where (R1+R2).gtoreq.2R2 and C2&gt;C1.
FIG. 5 shows the magnitude of an impedance versus frequency plot. As shown in FIG. 5, the impedance Z(s) first exhibits a low frequency value equal to Re1, then reduces to a value equal to Re1 in parallel with Re2 for mid-band frequencies, and finally approaches zero as the frequency is increased towards infinity.
The breakpoints in the impedance versus frequency curve of FIG. 5 represent the designed poles and zeros for the equalization amplifier shown in FIG. 1. The transfer function for the equalization amplifier is given by substituting EQ. C into EQ. A. Using the component variables from FIG. 1, the transfer function can be described by: ##EQU4## where .tau..sub.z1 =Ce2(Re1+Re2), .tau..sub.z2 =Ce1.multidot.Re1.multidot.Re2/Re1+Re2, and .tau..sub.p1 =Re2Ce2.
Thus, by correctly positioning the pole and the two zeroes, a good compensation for one length of transmission line can be created.
Although a good approximation of the inverse transfer function of one length of transmission line can be created by correctly selecting the component values for resistor Re1, resistor Re2, capacitor Ce1, and capacitor Cs2, the same component values will not adequately compensate for other lengths of transmission line. Thus, there is a need for an equalization amplifier which can adaptively accommodate different lengths of transmission line.
FIG. 6 shows an equalization amplifier 8 illustrating the equalization amplifier of FIG. 1 with a variable resistor Rv. As shown in FIG. 6, variable resistor Rv is positioned between the emitter of input transistor T1 and both capacitor Ce1 and the series connection of transfer resistor Re2 and capacitor Ce2. In operation, by varying the resistance of variable resistor Rv via a control signal Vec, the transfer function produced by the adaptive equalization amplifier changes.
Adaptive equalization amplifier 8, however, suffers from bandwidth limitations and implementation problems for a monolithic integrated circuit. As the variable resistor Rv is increased to accommodate a less lossy or shorter transmission line, a second pole is created which moves down in frequency, thereby limiting the high-frequency bandwidth. The bandwidth, therefore, is no longer independent of the correct positioning of the single pole and the two zeros. In addition, the parasitic capacitance associated with an appropriately sized JFET or MOSFET used to create the variable resistor, combined with the temperature and manufacturing variability of such components, presents a serious implementation problem for this circuit in practical monolithic integrated circuit form.
A Fiber Distributed Data Interface (FDDI) network is a local area network that provides a high bandwidth interconnection among computers and peripheral equipment using both fiber optics and copper as the transmission medium. The symbols are transmitted synchronously at a rate of 125 Megasymbols per second. An asynchronous transfer mode (ATM) network is a local area network which also provides a wide bandwidth interconnection among computers. ATM symbols are sent at a rate of 156 Mega-symbols per second.
Thus, the preferred bandwidth for an adaptive equalization amplifier utilized in a copper FDDI or ATM network is in excess of 156 MHz. When the FIG. 6 example is utilized in an FDDI network with worst case transmission lines shorter than approximately 100 meters, the second pole falls below the bandwidth required for the maximum data rate.
Thus, there is a need for an adaptive equalization amplifier which can accommodate variable length transmission lines without limiting the bandwidth of the data signal and which can be reliably produced using monolithic integrated circuit processing.